2018-09-03

I know I’ve said it before, but I will go ahead and say it again: the end is in sight.  In the last few days I’ve addressed the last few remaining issues:

1. Persistent offset on analog input #8 (ICD4)

Turned out to be an input voltage offset issue.  See here for more details.

2. ADC input weirdness on analog inputs 4-8 (ICD inputs)

The short version is that the op amp output is at approximately 5mV due to the voltage offset issue above.  Given the 5mV input into the ADC it still produces an output of 0.  This is outside of the absolute error spec for the ADC.  I suspect that this has something to do with the low reference to the ADC.  I’m using the VrefL pin for an ADC input and I am configuring the ADC low reference to use VSS, which is a perfectly valid configuration, but it’s weird to me that I’m off off zero by almost exactly the input on the VrefL pin.  I suspect a silicon bug, but can’t think of a way to prove it.  I’ve tried deliberately mis-configuring the ADC and it causes it to stop working leading me to believe that I have it configured properly.  It’s just weird that the ADC output is off by my input voltage offset.  If I do another run of boards I will bind the VrefL pin to ground and move that one input to a different pin.  Maybe.  The firmware calibration addresses the offset just fine.

3. ADC operational change

I have changed the ADC sampling from a free-running to triggered by a timer.  This was done during the troubleshooting of the above and in order to facilitate the item below.  I was experimenting to see if ADC accuracy was in any way correlated to the T_AD period.  The answer is no: not unless you reduce the T_AD bellow value specified in the data sheet.  I have left it that way because it does offer us more tunning knobs.  Even though we will probably never need to adjust them again.  The final configuration is sampling each analog input four times per second.  The processor gets interrupted every eight conversions or four times per second.

4. ADC reading sanity checking

One of the issues I discovered during all of this is that my calibration stuff was a bit broken.  For example, if an input was calibrated to +4 at a given voltage input, the reading would remain at +4 with a sensor disconnected.  Likewise if an input was calibrated to -4 the reading would underflow with the sensor disconnected.  I implemented the sanity checking in the ADC conversion ISR and that caused enough of delay where processor ground to a halt due because I had decreased the T_AD (see above).  Once I reduced the frequency of ADC conversions the problem was resolved.

5. HVAC_LIB/LOGIC_CORE board reset issue

There was an issue in the HVAC_LIB code that is used by LOGIC_CORE that failed to properly detect a board reset when the software was run against a board that had just been hard-reset.  This caused the output verification messages to not be emitted by the software which resulted in the board clearing the digital outputs.  This is part of the safety mechanism built into the board.  If the board does not receive a confirmation approximately every 10 seconds that the software wants to keep the outputs energized, the board clears the digital outputs.  This is to prevent equipment being kept on in perpetuity when (not if!) the controlling software crashes.

That’s it for now.  I will continue playing with all of the pieces, but as of right now the board has all of the functionality that I want and no bugs that I can’t live with.

Next step is tagging the firmware as a release and uploading the hardware designs to my GitHub.